Combined architecture of an analog-to-digital converter with balanced throughput–cost trade-off

Oleksiy Azarov, Oleksandr Dudnyk, Maksym Obertiukh, Oleksandr Lukashuk, Oleksandr Murashchenko

Abstract


The object of research in this article is a combined architecture of analog-to-digital converters (ADCs), which is built by integrating a low-resolution flash ADC with a successive approximation register (SAR) ADC. Flash ADCs provide extremely high conversion speeds but suffer from a significant drawback: the resolution cost per bit increases exponentially with increasing bit depth. In contrast, SAR ADCs are characterized by low cost per bit, but their inherently sequential conversion mechanism limits their conversion speed. This study investigates a combined ADC architecture designed to effectively merge the advantages of flash and SAR ADCs, thereby maximizing economic efficiency per resolution bit. The core hypothesis is that using a flash ADC of relatively low resolution for initial rapid coarse conversion, followed by a SAR ADC for precise computation of the residual analog signal, can significantly reduce the overall cost of implementing high-resolution ADCs. The research objectives include analyzing the characteristics of flash and SAR ADCs, determining the optimal combination of their respective resolutions, developing the operational algorithm of the proposed combined ADC, creating a mathematical model in MATLAB Simulink, and evaluating its technical and economic performance. The results demonstrate that the optimal combination is a flash ADC with a resolution of 4–5 bits paired with an 8–10-bit SAR ADC. This configuration significantly lowers the cost per bit compared with traditional high-resolution flash ADCs while maintaining a considerably higher conversion speed compared with SAR ADCs of equivalent resolution. The simulation results indicated that integral nonlinearity (INL) and differential nonlinearity (DNL) values of the proposed ADC did not exceed ±0.5 LSB, confirming high conversion accuracy. In addition, we show that the energy-per-conversion figure remains unchanged relative to pure flash and pure SAR solutions in isolation. Furthermore, the economic analysis demonstrated that the proposed combined approach minimizes the implementation costs per unit of resolution. Conclusions. The proposed combined ADC architecture demonstrates substantial economic benefits compared with conventional flash ADCs and notably improved speed characteristics compared with SAR ADCs. The resolution distribution between flash and SAR components efficiently balances economic and technical requirements. Further studies should focus on the practical implementation of the proposed ADC architecture, noise impact analysis, and adaptive resolution management strategies.

Keywords


: analog-to-digital converter; flash ADC; SAR ADC; combined architecture; energy efficiency; cost per bit; nonlinearity

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DOI: https://doi.org/10.32620/reks.2025.4.18

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