RADIOELECTRONIC AND COMPUTER SYSTEMS

The principle of program control means that the processor core turns to the main memory of the computer for operands or instructions. According to architectural features, operands are stored in data segments, and instructions are stored in code segments of the main memory. The operating system uses both page memory organization and segment memory organization. The page memory organization is always mapped to the segment organization. Due to the cached packet cycles of the processor core, copies of the main memory pages are stored in the internal associative cache memory. The associative cache memory consists of three units: a data unit, a tag unit, and an LRU unit. The data unit stores operands or instructions, the tag unit contains fragments of address information, and the LRU unit contains the logic of policy for replacement of string. The missing event attracts LRU logic to decide for substitution of reliable string in the data unit of associative cache memory. The pseudo-LRU algorithm is a simple and better substitution policy among known substitution policies. Two options for the minimization of the hardware for replacement policy by the pseudo-LRU algorithm in q - directed associative cache memory is implemented. The transition from the trigger structure of the synchronous D-trigger to the trigger structure of the synchronous JK-trigger is carried out reasonably in both options. The first option of minimization is based on the sequence for updating of the by the algorithm pseudo LRU, which allows deleting of the combinational logic for updating bits of LRU unit. The second option of minimization is based on the sequence for changing of the q - index of direction, as the consequence for updating the bits of LRU unit by the algorithm pseudo LRU. It allows additionally reducing the number of memory elements. Both options of the minimization allow improving such characteristics as productivity and reliability of the LRU unit.

algorithm pseudo LRU; type of trigger structure; associative memory cache; LRU unit; assessment of complexity by Quine

Omran, Safaa S., Amory, Ibrahim A. Implementation of LRU Replacement Policy for Reconfigurable Cache Memory Using FPGA. International Conference on Advanced Science and Engineering, Kurdistan Region, Iraq, November, 12-14, 2018. pp. 13-18.

Sudarshan, T. S. B., Mir, Rahil Abbas., Vijayalakshmi, S. Highly Efficient LRU Implementations for High Associativity Cache Memory. Birla Institute of Technology and Science, Pilani, Rajasthan 330331 INDIA, 2017. Available at: http://www.semanticscholar.org/paper/Highly-efficient-LRU-implementations-for-high-cache-Sudarshan-Mir/e9a6b5b9cb70fc3782b2709ebcf1414051ed6e4c (Accessed 2004)

Puidenko, Vadym., Kharchenko, Vyacheslav. The Minimizating of Hardware for Implementation of Pseudo LRU Algorithm for Cache Memory. The 11th IEEE International Conference on Dependable Systems, Services and Technologies, DESSERT’2020, 14-18 May, 2020, Kyiv, Ukraine, pp. 63-71.

Khan, Burhan Ul Islam., Olanrewaju, Rashidah F., Mir, Roohie Naaz., Khan, Abdul Raouf., Yusoff, S. H. A Computationally Efficient P-LRU based Optimal Cache Heap Object Replacement Policy. International Journal of Advanced Computer Science and Applications, vol. 8, no. 1, 2017, pp. 128-138.

Kumar, Swadhesh., Singh, P. K. An Overview of Modern Cache Memory and Performance Analysis of Replacement Policies. 2nd IEEE International Conference on Engineering and Technology, India, 2016, pp. 4145-4148.

Alghazo, Jaafar., Akaaboune, Adil., Botros, Nazeih. Cache Replacement Algorithm Records. International Workshop on Memory Technology, Design and Testing, Illinois, USA, August, 2004, pp. 19-24.

Reineke, J., Grund, D., Berg, C., Wilhelm, R. Timing predictability of cache replacement policies. Real-Time Syst., vol. 37, no. 2, Nov. 2007, pp. 99-122.

Pukhalskiy, G. I, Novoseltseva, T. Ya. Proektirovanie diskretnykh ustroistv na integral'nykh mikroskhemakh: Spravochnik [Designing discrete devices to integrated circuits: Directory]. Moscow, Radio i svyaz’ Publ., 1990. 304 p., pp. 61-91.